The present disclosure relates to a spread-spectrum clock generator.
Phase-locked loops (PLLs) are generally employed in most digital systems operating synchronously. With improvements in technology, digital systems are evolving in operation frequency and integration density, and PLLs are evolving as well. The high-speed development of the digital systems and PLLs is usually accompanied by the adverse effect of electromagnetic interference (EMI). EMI may be induced when an energy level is over a predetermined reference value, adversely affecting peripheral electronic devices and causing malfunctions therein. In particular, because semiconductor devices are highly sensitive to EMI, it should not be neglected in designing semiconductor integrated circuits.
For the purpose of reducing EMI, there is a technique that utilizes a spread-spectrum clock generator. More specifically, the spread-spectrum clock generator acts to reduce EMI, by modulating a reference signal, which has high energy at a specific frequency, into a signal that operates in a predetermined bandwidth and has lower energy than the reference signal at a frequency of the bandwidth. As an example, if the reference signal frequency is 3 GHz, the spread-spectrum clock generator conducts the modulation operation to cause the signal to vary between 3 GHz and 2.97 GHz for predetermined repeating cycles.
As such, a clock signal from a PLL is modulated to vary in a predetermined range of frequency, not to be fixed to a single frequency, thereby becoming a signal not affecting peripheral electronic devices by EMI, because the energy of the clock signal disperses at a specific frequency.
The spread-spectrum clock generator operates to reduce a power gain by step-wise modulating a clock frequency of the PLL. Therefore, the spread-spectrum clock generator is a so-called clock generator for lessening the adverse effect of EMI.
FIG. 1 at (a) through (f) shows reference frequency variations of a general PLL output signal and an output signal obtained by using the spread-spectrum clock generator. FIG. 1(a) shows a clock signal oscillating at a regular frequency without using the spread-spectrum clock generator. FIG. 1(b) shows a frequency spectrum having a center frequency peak over a predetermined energy level P0, generating the effect, of EMI at a reference frequency, 3 GHz. FIG. 1(c) shows a frequency variation of the PLL output signal over time, oscillating at the regular reference frequency. FIG. 1(d) shows a clock signal oscillating at a variable frequency, using the spread-spectrum clock generator. FIG. 1(e) shows a frequency spectrum spreading with a peak power less than the predetermined energy level P0, dispersing around the reference frequency. FIG. 1(f) shows a frequency variation of an output signal over time. As described above, the frequency is modulated to vary between 3 GHz and 2.97 GHz.
Generally, the process of measuring jitter is carried out on a spread spectrum clock signal that has experienced clock data recovery (CDR). If there is jitter over a bandwidth of CDR while generating the spread spectrum clock signal, however, the jitter remains therein, and is not filtered through the CDR.
FIG. 2 shows a spread spectrum clock signal produced by a general spread-spectrum clock generator. Referring to FIG. 2, the general spread-spectrum clock generator produces an abrupt change of phase. For that reason, there is jitter having a high frequency while generating a spread-spectrum clock. That high-frequency jitter cannot be filtered by a CDR process at a reception stage. Therefore, there is a problem that the jitter still remains even after the CDR.